Gaming machine critical data memory system and method

ABSTRACT

A gaming machine with a critical data memory system is provided for high speed and permanent storage and retention of critical data. The gaming machine includes high speed NV-RAM queue memory for secure, temporary storage of critical data and mass storage permanent memory for long term, secure storage of critical data. Additionally, operating procedures for storing, verifying, and correcting the stored critical data are provided.

BACKGROUND OF INVENTION

In the gaming industry, many advances have been made in gaming machines and their electronics. The evolution has been from a mechanical device, e.g., slot machines, to totally electronic machines having computer technology contained within the gaming machine. The use of fully electronic gaming machines results in better control over their operation, the ability to offer a wide variety of games in the same machine and the ability to gather and store data, commonly referred to as critical data, regarding the operation the gaming machine. Laws in many jurisdictions require the gathering and retention of certain critical data for various periods of time up to and including several years. These data may include financial accounting information, machine and game state information, game play history, player tracking information, all configuration settings, and any other data requiring secure, long term storage.

The collection and storage of critical data can be problematic. There are two basic types of memory, volatile and non-volatile memory. The data in volatile memory disappears when the memory device is no longer powered. Non-volatile memory will retain data in storage if normal power is lost. Some non-volatile memory use a battery backup to make the memory non-volatile while other forms of memory do not require battery backup or power to retain data in memory, e.g., certain types of flash drives and so called hard drives.

In memory devices, there are various forms of RAM memory which are very effective for storing and handling information quickly. However, even though the price is being reduced, RAM memory can be relatively expensive but it is highly effective in the fast processing of memory transactions. Mass storage media is also well known, e.g., what are commonly referred to as hard drives using magnetic disk media for storage of data in a permanent manner. Although storage capacity for hard drive devices far exceeds RAM devices, memory transactions to and from hard drives require considerably more time than RAM.

The gaming machine may also include a processor such as a CPU (central processing unit) where data may be manipulated for various purposes, e.g., verification, rewriting, calculation and to provide directions for storage. Graphics and sound drivers may be included in the processor or may be separate therefrom as cards. The cards or drivers are adapted to provide signals to a display such as an LCD screen for viewing or speakers for listening by a player.

Controller devices are also provided on a gaming machine for controlling the operation thereof by a player. Also, payment means are provided, e.g., coin or paper money slots, credit card readers and the like as are known in the art.

While such gaming machines are generally well known, they do have deficiencies. One deficiency is the ability to store and verify data while allowing the gaming machine to run at high speeds with no noticeable pauses by the player. U.S. Pat. Nos. 7,111,141 and 6,804,763 address this issue by providing non-volatile RAM for data storage device which allows both for the long term storage of critical data and other data which permit operation of the gaming machine. However, long term storage of large quantities of data is difficult in such RAM storage and even though they are constructed to be non-volatile e.g., by having battery back-up, they could still fail and lose data or run out of storage space.

Thus, there is a need for an improved critical data storage and processing architecture for gaming machines.

SUMMARY OF INVENTION

The present invention involves the provision of a gaming machine and method of operation to effect high speed and permanent storage of gathered critical data. Critical data are first stored in a memory queue constructed from non-volatile, high speed memory device, e.g., non-volatile RAM and may be stored in a plurality of separate formats. Critical data are then transferred to secondary non-volatile permanent memory, e.g., a hard drive, capable of mass storage of data. The high speed memory device may be constructed to be redundant in separate memory devices as can be the mass data storage device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a perspective view of a gaming machine.

FIG. 2 is a schematic illustration of various hardware components used in a gaming machine.

FIGS. 3A-3H are flow charts illustrating the critical data writing operations of the gaming machine.

FIGS. 4A-4I are flow charts illustrating critical data reading operations of the gaming machine.

Like numbers throughout the various figures designate, like or similar parts or operation.

DETAILED DESCRIPTION

As seen in FIG. 1, the gaming machine 1 includes a cabinet 2 for enclosing various of the components 3 (FIG. 2) of the gaming apparatus. The gaming machine 1 includes a video display 4 which may be in the form of a CRT or LCD screen or the like. A set of controls 5 is also provided to allow the player to operate the gaming machine 1 and may include a joy stick, buttons or combinations thereof. The video display 4 may include a touch screen for player interaction. Means 7 is provided in the gaming machine 1 for the receipt of payment. Payments may be made with cash in the form of coins or bills, credit slips, tokens and credit or debit cards. The gaming machine 1 is also provided with a payout device 9 which can be in the form of a device for printing a receipt, delivery of cash, a credit to be put on a credit type card or the like.

Portions of the electronics 3 are shown in FIG. 2. The electronics 3 include a data processor 11, such as a CPU, which may also include a video interface and other device interfaces built into the processor. Separate interface components may also be provided if desired, which separate interface components would be linked to the processor 11 as is known in the art. A memory controller 12 is connected to the processor 11 and interfaces high speed memory devices 14 such as a one or more DRAM modules. The memory controller 12 may be integrated into the processor 11 if desired. The electronics that comprise the critical data memory system 15 preferably include at least two forms of fixed or secure critical data memory system devices. The first form of secure memory is preferably a high speed non-volatile RAM (NV-RAM) memory 16 and the other form is preferably a permanent mass data storage device 17 which needs no electrical backup power to maintain stored data. Such a mass data storage device can be a hard disk, flash memory or the like. The NV-RAM 16 may be a solid state device such as a D-RAM or S-RAM chip with a battery backup 31. The memory 16 could also be high speed flash or the like. The memory 16 is preferably fast in operation compared to current permanent storage devices, although fast permanent storage devices may be provided. In a preferred embodiment, the secure memory 15 includes NV-RAM 16 in the form of battery backed-up SRAM and the permanent memory devices 17 are magnetic hard disk drives. In a preferred embodiment, the total storage capacity of the memory 16 is at least about 1 MByte and preferably at least about 4 MBytes. The memory 17 has a total storage capacity of at least about 80 GBytes and preferably at least about 200 GBytes. Additional capacity is acceptable and will be determined by the game or games capable of being played on the gaming machine 1, as well as the required amount of storage which will be determined by the amount of program and critical data needed to be stored, and the duration that data must be stored. Although redundant memory storage devices 16A, B and 17A, B are shown, one each may be used if desired. However, extra security in data storage can be achieved by the use of multiple memory devices. The memory devices 16, 17 can communicate through an appropriate I/O controller hub 21 as are known in the art. The electronics may also include a firmware hub 22, PCI bridge 23, video port 24, video subsystem 25, USB port(s) 26 networking port(s) 27, audio hardware 28, hard disks controller 28 and a general purpose I/O 29.

Software, including an operating system e.g., Windows, available from Microsoft, and game application software are utilized to control the various operations of the various devices including the processor 11, and the memory devices 14, 15.

The high speed memory devices 16 serve as a queue similar to a memory cache. Data can be quickly written to and read from the high speed memory via the gaming machine's circuitry. Each time a significant event such as a game commencement or a game completion occurs, the state of the gaming machine is stored (written) in critical data secure memory system 15 and often immediately retrieved (read) for a verification on accuracy. The processor 11 provides data to the memory 15 and retrieves data from the memory 15. The processor 11 may also process the information in the memory 14 for such things as accounting purposes, game scores, game outcomes, game starts, and other critical data before writing to the memory 15. The power sources 31 e.g., batteries, provide data retention power to the memory devices 16 in the event the main power is terminated thereby maintaining the information in the memory 16 secure.

As programmed, the processor 11 will from time to time extract data from the memory 14 and transfer it to the secure memory 15. However, during the process of verification, the information in the memory 14 is retained and not deleted or written over until verification is confirmed. In a preferred embodiment, each type of memory in the secure memory system 15 is structured with at least two physical banks or device components. Preferably, memory devices 16A, 16B are similarly constructed and contain copies of the same critical data to provide security for the data until verification is performed and confirmed. Furthermore, each of the memory devices 16A, 16B is similarly configured preferably in three logical sections or segments (1), (2), (3) and tested for equivalence. In memory segments 16A(1) and 16B(1), a precise copy of the critical data are held in the queue. In memory segments 16A(2) and 16B(2), an inverted copy of the critical data are maintained. Segments 16A(3) and 16B(3) contain the results of mathematical operations on the critical data such as check sums or cyclical redundancy checks (CRC's) of the data.

The queue can be addressed and accessed by the processor 11 by any conventional means, including the processor's local data and address bus, or through a standard expansion bus such as an ISA (Industry Standard Architecture) or PCI (Peripheral Component Interconnect). Because of the high speed operating nature of the memory 16, only a very short period of time, too short to be noticed by a game player, the gaming machine software can write the critical data to the queue, read it back for a check on accuracy and then continue normal operation with certainty that the critical data will not be lost.

The critical data memory system 15 described above can also be made to appear as a virtual disk by an appropriate device driver. The virtual disk may be partitioned and formatted with a file system. The resulting virtual disk is used for storage of the critical data as described above.

To the operating system and any software application running on the gaming machine 1, the virtual disk functions as an ordinary disk combining the high speed queue with a large capacity mass media memory device. The device driver software ensures that every sector that is written to the virtual disk is stored in a fault tolerant manner. The device driver also manages the task of transferring data between the queue and the permanent memory device. Additionally, when data are read from the virtual disk the device driver utilizes the redundant copies in the memory 16 queue or on the memory device 17 to detect and correct any errors or data loss that may develop.

Referring now to FIGS. 3A-3H, after the critical data are written 51 to the queue in memory 16 and read-back for a check on accuracy, a separate background software task in the driver transfers data 52 from the queue to the mass storage device 17 as described below. Preferably, there are at least two mass storage memory devices 17A, 17B which have permanent memory to provide for redundancy. The data contained within the queue is not removed or deleted at this time. A verification step ensures that the data are copied without error to one or more of the memory devices 17A, 17B prior to removal from the queue. Once data are securely stored in the permanent memory, the memory space in the queue can be freed up and made available for the next critical data transaction. Speed of operation is enhanced by use of the queue because critical data can be quickly written to the queue and then later transferred to the permanent memory in the background by a low priority task. Delay in the overall performance of the gaming machine 1 is reduced to a point where there is no visible hesitation seen by the player.

In a preferred embodiment, the permanent memory 17 is a redundant memory preferably having at least two permanent memory devices 17A, 17B such as two hard disk drives. In a preferred embodiment, the two hard disk drives are a master and a slave.

Having two permanent memory devices 17 provides redundancy. The permanent memory devices may both be contained within the gaming machine 1 or one may be contained in the gaming machine 1 and one being remote or both may be remote from the gaming machine.

In the case of the permanent memory devices 17 being hard disk drives, the disk drives may be partitioned into two or more logical sections. At least one of the those sections on each of the disk drives may be dedicated to the storage of critical data. The critical data may be stored in one or more disk directories and in one or more files or subfiles in each directory in each of the hard disk memory devices. In a preferred embodiment, each of the hard disks 17A, 17B contain a plurality and preferably three identical copies of the critical data file making a total of six copies, three on each memory device 17A, 17B. In a preferred embodiment, the use of three copies on each device 17 allows for a voting scheme to be used for validating the stored critical data. When the data from at least two copies are found to match, the stored critical data are considered accurate and if necessary can be used to correct a corrupted file in either or both of the memories 17A, 17B or the memories 16A, 16B.

By the use of a plurality of permanent memory devices 17, one can be replaced in the gaming machine (or in a remote location) with no loss of historical critical data information. Additionally, one or more of the memory devices 17 may be used to contain the gaming machine 1 controller software. As such, the software can be replaced or upgraded to a newer version or replaced with the same version with no loss of historical critical data information.

The memories 16A, 16B and the memories 17A, 17B contain duplicate copies of the critical data and non critical data where appropriate, and contain multiple copies in each memory device.

The following is a description of the critical data write algorithm illustrated in FIGS. 3A-3H. When a critical data component is written to the queue, the non-inverted version is first written 51A and then the inverted version 53A is written, then the verifier version 54A is written. By completing all of the writes to memory before the reads, the device driver software can detect any possible overlapping of the data. Overlapping is an electrical fault that causes data in one location to be altered by reads or writes to another location. The critical data are then similarly written 51B, 53B, 54B to the memory device 16B, FIG. 3A.

Read-backs of each section are performed to ensure accuracy. The verifier data are read back 56A, 56B and data from each of the sections are checked 55. In a similar fashion read-backs are performed on the inverted copy 58A, 58B in sequence and the non-inverted copy 59A, 59B. Any errors found in the read back data are logged as write errors in the appropriate memory section and corrected 57A, 57B, 60A, 60B, 61A, 61B. FIGS. 3B, 3C. If the error correction algorithm, FIG. 3G, is unsuccessful at correcting an error after a specific number of tries, the system takes appropriate action such as disabling the gaming machine. A signal may be sent to an appropriate receiver that the gaming machine is being disabled preventing continued play.

After it has been determined that the data were properly written to the memory queue 16, a determination 62 is made if the system is able to allow a low priority task transfer of data from the queue to the memory devices 17. If the answer is yes, the device driver writes a copy 63A of the file data to the critical data disk file 1 on the master memory device 17A. The device driver then writes a copy 63B of the file data to the critical data disk file 2 on the master memory device 17A. The device driver then writes a copy 63C of the file data to the critical data disk file 3 on the master memory device 17A. Then in the same sequence, the device driver writes a copy of the file data to the critical data disk files 1, 2 and 3 on the slave memory device 17B as shown in steps 64A, 64B, and 64C.

After the data have been written to the disk files as described above, the device driver reads back file data and if needed corrects the data stored on the master and slave memory devices 17A and 17B. The device driver begins by reading back data 65A from the data disk file 3 on the master memory device 17A. If the data are incorrect an error correction 66A is performed on the critical data in disk file 3 on the master memory device 17A. The process for correcting errors is shown in FIG. 3H. If the data are correct, or have been corrected, then the device driver reads back file data 65B from data disk file 2 on the master memory device 17A. If the data are not correct, error correction 66B is performed. If the data are correct, or have been corrected, then the device driver reads 65C from the disk file 1 on the master memory device 17A. If the data are incorrect, error correction 66C is performed. If the data are correct, or have been corrected, the data on the master memory device 17A have now been verified. In the same fashion, data from the slave memory device 17B are read back, checked and, if necessary, corrected as shown in steps 67A, 67B, 67C, 68A, 68B, 68C, 55 FIGS. 3E and 3F. After this, the critical data file information in the queue memory devices 16 may be erased or the space made available 70 for overwriting. The device driver has now successfully completed a write operation 71 to the critical data virtual drive.

FIGS. 3G and 3H show error correction procedures used if an error is detected during any of the read-backs performed as part of the critical data write operation. FIG. 3G shows the error correction procedure for data stored in a memory device 16 and FIG. 3H shows the error correction process for data in the memory device 17. Both processes are similar except for the memory device storing the data which are being corrected. A description of the process regarding FIG. 3G also applies to the process shown in 3H. The device driver has encountered an error 72 during a read back operation on a section of one of the memory devices. The error is logged 73. The device driver rewrites data 74 to the appropriate section of the memory device. The device driver reads back the data 75 from the desired section of the memory device. If the read back data are correct then the error is corrected and the program continues with the read back algorithm 76. If the read back data were not correct and it was a third attempt to correct an error then an uncorrectable error is declared 77 and operation of the gaming machine is halted. If the attempted correction is not the third attempt, then the process is repeated until the third attempt is made at correcting the error 78.

If an error is detected during a device driver critical data read operation, the system preserves all the existing, new unverified critical data. The critical data that are eventually voted out may be written over during a repair process. When critical data are read from storage the underlying data are read from one or more active memory devices, e.g., the non-volatile memory devices 16 and/or permanent memory devices 17. If there are two or more active memory devices 16, 17, their data are compared. If the data in the two or more active memory devices 16, 17 match, those sections are allowed to participate in the voting scheme. One outcome of the voting is that the data matches between the various files in the various memory devices and the critical data is accepted and provided to the operating system by the device driver. If any of the sections in the memories 16 do not match the others, a repair algorithm is run. The first stage of the repairs is finding what data should actually be stored. Sections 1 and 2 in the memory 16A are compared and then section 1 and the verifier are compared and finally section 2 and the verifier are compared. Section pairs that match participate in voting. If verifiable data are not found, the system reads the three sections from the alternate memory device 16B and repeats the voting scheme. If no verifiable data are found, the read fails. Eventually the system either determines accurate data or disables the gaming machine 1. After a data error has been detected all of the sections in the memory devices 16A, 16B are checked and repaired and the entire read procedure is repeated. If the critical data are found to be accurate, the critical data are accepted and provided to the operating system by the device driver.

FIG. 4 including sheets 4A-4I illustrates this process of the device driver reading critical data from the memory 15. When the operating system initiates a read from critical data memory 15, the device driver first must determine if the data are resident in the queue memory or in the permanent memory 17. This determination 79 is shown in FIG. 4A. The process of reading and verifying the data is the same whether it is being read from the queue memory 16 or the permanent memory 17. For convenience, since the memory 16 and the memory 17 are shown in the preferred embodiment as each having banks A and B, the read process will be described in terms of bank A and bank B with both relating to the memory 16 or the memory 17.

If there is a third successive attempt to read data following a repair operation then the gaming machine operation is halted 80. If it is not the third attempt then the device driver reads data 81 from bank A section 1 and bank B section 1. If the data read from bank A section matches the data read from bank B section 1 then the device driver reads data 82 from bank A section 2 and bank B section 2. If data from section 2 of bank A and bank B match, then the data from bank A sections 1 and 2 are compared 84 to the data from bank B sections 1 and 2. If a match is found, then the device driver reads data 85 from bank A section 3 and bank B section 3. If the section 3 data match 86 then a comparison 87 is made to determine if the data from bank A sections 1 and 2 match the data from bank B section 3. If the answer to this comparison is yes, then the device driver provides data 88 read from sections 1 of bank A and B and has now successfully completed a read operation from the critical data virtual drive. If the answer to any of the comparisons is no, then one section may require a repair operation 89. To determine which section requires repair, the device driver first reads data 90 from bank A section 1 and bank B section 1. A determination is made 91 whether or not the data from bank A section 1 match data from bank B section 1. If a match is found, then the device driver reads data 92 from bank A section 2 and bank B section 2. If these data match 93 then a determination is made 94 if data in bank A sections 1 and 2 also match data from bank B sections 1 and 2. If the answer is yes, then an error correction procedure is performed 95 on section 3 of the memory and the entire read operation is restarted on FIG. 4B. If the answer is no, then section 1 or section 2 may require repair operation 96. To do this repair, the device driver begins by reading data 98 from bank A section 1 and bank B section 1. If the data matches 99, then the device driver reads data 100 from bank A section 3 and bank B section 3. If the data matches 101 then the determination is made 102 if the data from bank A sections 1 and 3 match data from bank B sections 1 and 3. If the answer is yes, then an error correction procedure is performed 103 on section 2 and the entire read operation is restarted on FIG. 4B. If the answer is no, then section 1 or section 3 may require a repair operation 104. A test is then performed to determine whether or not sections 2 and 3 are without error which would result in section 1 requiring a repair operation 106. The device driver reads data 107 from bank A section 2 and bank B section 2. A determination is made 108 if bank A section 2 data matches data from bank B section 2. If the answer is yes, the device driver reads data 109 from bank A section 3 and bank B section 3. A comparison is made 110 to determine if bank A section 3 data matches data from bank B section 3. If the answer is yes, then a comparison is made 111 to determine if bank A sections 2 and 3 data match data from bank B sections 2 and 3. If the answer is yes, then an error correction procedure 112 is performed on section 1 and the entire read operation is restarted on FIG. 4B. If the answer is no, one bank may require a repair operation 113. To effect repair, a test is performed to determine which bank may be defective. The device driver reads data 115 from bank A sections 1, 2 and 3. A determination is made 116 if the data in sections 1, 2 and 3 of bank A match. If the answer is yes, the device driver reads data 117 from bank B sections 1, 2 and 3. A determination is made 118 if sections 1, 2 and 3 of bank B match. If the answer is yes, a determination is made 119 to determine if bank A data completely match bank B data. If the answer is yes, then it has been determined 120 that bank A and bank B appear to have no errors and the read operation is then retried. The above process may then be recycled by starting the process as shown in FIG. 4B. However, if the comparison in step 119 is negative, then a conclusion is made 121 that bank A or bank B appear to have spurious errors and the gaming machine is halted 122. If the data in sections 1, 2 and 3 of bank B do not match 118, an error correction procedure is performed 126 on bank B by starting the process as shown in FIG. 4I and, if the error correction procedure is successful, then the entire read operation is restarted on FIG. 4B. If the data read from bank A sections 1, 2, and 3 do not match 116, then the device driver reads data 127 from bank B sections 1, 2, and 3. A determination is made 128 if the data in sections 1, 2, and 3 of bank B match. If the answer is yes, then an error correction procedure 129 is performed on bank A as shown in FIG. 4I and, if the error correction procedure is successful, then the entire read operation is restarted on FIG. 3B. If the data in sections 1, 2, and 3 of bank B do not match then a determination has been made 131 that both banks A and B have returned errors. If this occurs, then the gaming machine is halted 132.

FIGS. 4H and 4I show error correction procedures. The procedure shown in FIG. 4H is a repair operation on one section using file data read and verified from two other sections. FIG. 4I shows a repair operation on one bank using data read and verified from the other bank.

The repair operation shown in FIG. 4H applies to any of the sections 1, 2, and 3 and is referred to generically as section X. To perform this operation, it has been determined that section X of bank A or bank B requires an error correction 141. A device driver writes a copy 142 of file data to bank A section X. The device driver then writes a copy 143 of file data to bank B section X. The device driver then reads back data 144 from bank A section X. A determination is made 145 if the read back data are correct. If the answer is no, then the gaming machine operation is halted 146. If the answer is yes, the device driver reads back data 147 from bank B section X. A determination is made 148 if the read back data are correct. If the answer is no, the operation of the gaming machine is halted 149. If the answer is yes, section X has been corrected and operation is continued 151.

FIG. 4I illustrates a representative repair operation on one bank using data read and verified from the other bank in this case, bank A and B are generically referred to as X. A determination has been made 156 that there is an error in bank X that requires correction. The device driver writes a copy 157 of file data to bank X section 1. The device driver then writes a copy 158 of file data to bank X section 2. The device driver writes a copy 159 of file data to bank X section 3. The device driver then reads back data 160 from bank X section 1. A determination is made 161 if the read back data are correct. If the answer is no, then operation of the gaming machine is halted 162. If the answer is yes, the device driver reads back data 163 from bank X section 2. A determination is made 164 if the read back data are correct. If the answer is no, then the gaming machine operation is halted 162. If the answer is yes, then the device driver reads back data 165 from bank X section 3. A comparison is made 166 if the read back data are correct. If the answer is no, gaming machine operation is halted 162. If the answer is yes, bank X has been corrected and operation is continued 167.

Thus, there has been shown and described several embodiments of a novel invention. As is evident from the foregoing description, certain aspects of the present invention are not limited by the particular details of the examples illustrated herein, and it is therefore contemplated that other modifications and applications, or equivalents thereof, will occur to those skilled in the art. The terms “having” and “including” and similar terms as used in the foregoing specification are used in the sense of “optional” or “may include” and not as “required.” Many changes, modifications, variations and other uses and applications of the present invention will, however, become apparent to those skilled in the art after considering the specification and the accompanying drawings. All such changes, modifications, variations and other uses and applications which do not depart from the spirit and scope of the invention are deemed to be covered by the invention which is limited only by the claims which follow. 

1. An electronic gaming machine comprising: a video output device; a play controller device; a processor connected to the video output device and the controller; and a memory system comprising at least one non-volatile memory device and at least one permanent memory device each operably associated with the processor said processor being programmed to effect storage of critical data in the non-volatile queue memory, write the critical data to the permanent mass-storage memory, verify the accuracy of the critical data in the permanent memory and when verified permit deletion and/or overwriting of the verified critical data in the non-volatile memory.
 2. The gaming machine of claim 1 wherein the memory system including at least two permanent memory devices.
 3. The gaming machine of claim 2 wherein at least one of the permanent memory devices including a disk drive.
 4. The gaming machine of claim 1 wherein the memory system including at least two non-volatile memory devices.
 5. The gaming machine of claim 4 wherein at least one of non-volatile memory devices including a solid state memory device.
 6. The gaming machine of claim 4 wherein at least two of said non-volatile memory devices each including a solid state memory device.
 7. The gaming machine of claim 1 wherein at least one said non-volatile memory device including a back-up power source.
 8. The gaming machine of claim 7 wherein the back-up power source including a battery.
 9. The gaming machine of claim 1 wherein the video output device including a display screen.
 10. The gaming machine of claim 1 wherein the play controller including at least one of a push button, joy stick and touch screen.
 11. The gaming machine of claim 1 wherein the non-volatile memory device and the permanent memory device being configured as a virtual memory device.
 12. The gaming device of claim 1 wherein there being at least two said non-volatile memory devices and at least two said permanent memory devices.
 13. A method of storing critical data on a gaming machine, the method including: generating critical data regarding operation of the gaming machine; writing at least a portion of the generated critical data to a first secure memory; writing the critical data stored in the first secure memory to a second secure memory thereby providing at least a first and a second set of the critical data; and comparing the set of critical data in the second secure memory to the set of critical data in the first secure memory and when the first and second sets of critical data are verified as being the same, permitting deletion and/or overwriting of the set of critical data in the first secure memory.
 14. The method of claim 13 including; generating a third set of critical data; writing the third set of critical to the first secure memory; writing the third set of critical data to the second secure memory to make a fourth set of critical data; comparing the fourth set of critical data to the third set of critical data and when the first and second sets of critical data are verified as being the same, permitting deletion and/or overwriting of the third set of critical data; and maintaining the second and fourth sets of critical data in said second secure memory for an extended period of time.
 15. The method of claim 14 including storing a plurality of copies of each of the second and fourth sets of critical data in the second secure memory.
 16. The method of claim 15 including storing a plurality of copies of each of the first and third sets of critical data in the first secure memory.
 17. The method of claim 15 including comparing each of the copies of the second and fourth sets of critical data to the first and second sets of critical data respectively and when two or more of the copies of respective sets of critical data are verified as the same then permitting the overwriting and/or deleting of the respective critical data sets from the first secure memory.
 18. The method of claim 13 wherein the first and second secure memories being configured as virtual memory.
 19. The method of claim 18 wherein the first secure memory including non-volatile ram and the second secure memory including permanent memory.
 20. The method of claim 19 wherein the permanent memory including at least one disk drive. 